DocumentCode
1150874
Title
A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing
Author
Fujiwara, Eiji ; Mutoh, Nobuo ; Matsuoka, Kohji
Author_Institution
Musashino Electrical Communication Laboratory, N.T.T.
Issue
6
fYear
1984
fDate
6/1/1984 12:00:00 AM
Firstpage
578
Lastpage
583
Abstract
This correspondence demonstrates a new kind of error-checking scheme for multioutput combinational circuits and its use for a built-in testing method. In the error-checking logic employed, the output from the circuits being checked is partitioned into several groups. The predicted group parity is compared to that produced from the output in each group. This checking circuit, called a group-parity prediction (GPP) checker, can be implemented systematically. To ensure that the GPP checker is self-testing, several conditions are required. The self-testing GPP checkers are implemented for some concrete examples of multioutput combinational circuits. With respect to these examples, the self-testing GPP checker shows 87-100 percent error detection ability, and 91-100 percent fault coverage for single stuck faults. Using this self-testing GPP checker, a self-verification testing method, which takes advantage of the automatic fault-detection capability of a checker, is shown to be applicable to testing combinational circuits.
Keywords
Built-in testing; duplication; error-detection ability; fault-detection ability; group-parity prediction checker; self-checking checker; self-testing; self-verification; Arithmetic; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Combinational circuits; Computer errors; Cyclic redundancy check codes; Error correction codes; Pattern matching; Built-in testing; duplication; error-detection ability; fault-detection ability; group-parity prediction checker; self-checking checker; self-testing; self-verification;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1984.1676486
Filename
1676486
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