• DocumentCode
    1150945
  • Title

    Computational Geometry on a Systolic Chip

  • Author

    Chazelle, Bernard

  • Author_Institution
    Department of Computer Science, Brown University
  • Issue
    9
  • fYear
    1984
  • Firstpage
    774
  • Lastpage
    785
  • Abstract
    This paper describes systolic algorithms for a number of geometric problems. For the sake of realism we restrict our investigation to one-dimensional arrays whose communication links with the outside are located at the end cells. Implementations yielding maximal throughput are given for solving dynamic versions of convex hull, inclusion, range and intersection search, planar point location, intersection, triangulation, and closest-point problems.
  • Keywords
    Analysis of algorithms; VLSI; computational geometry; convolution; parallel computation; pipelining; real-time algorithms; systolic arrays; Algorithm design and analysis; Circuits; Computational geometry; Computer science; Concurrent computing; Costs; Pipeline processing; Systolic arrays; Throughput; Very large scale integration; Analysis of algorithms; VLSI; computational geometry; convolution; parallel computation; pipelining; real-time algorithms; systolic arrays;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.1984.1676494
  • Filename
    1676494