Title :
Fault-Tolerant Multiprocessor Link and Bus Network Architectures
Author :
Pradhan, Dhiraj K.
Author_Institution :
Department of Electrical and Computer Engineering, University of Massachusetts
Abstract :
This paper presents a general class of regular networks which provide optimal (near-optimal) fault tolerance.
Keywords :
Algorithmic routing; circuit switching; connectivity; diameter of graphs; fault-tolerant communication network; multiple bus network; multiprocessor networks; packet switching; regular graphs; regular networks; shared-bus fault tolerance; shuffle-exchange graph; Binary trees; Circuit faults; Computer architecture; DH-HEMTs; Degradation; Fault tolerance; Fault tolerant systems; Packet switching; Routing; Switching circuits; Algorithmic routing; circuit switching; connectivity; diameter of graphs; fault-tolerant communication network; multiple bus network; multiprocessor networks; packet switching; regular graphs; regular networks; shared-bus fault tolerance; shuffle-exchange graph;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1985.1676513
