A technique for the design of microprocessor memory systems

A systematic technique for the design of the chip select logic for microprocessor memory systems is given. In this technique, a memory table must be completed that shows the logic levels on each address line required to place every device (RAM, ROM, and I/O ports) at their desired locations in memory space. The memory table helps a designer visualize the system requirements and properly design the address decoding logic. The possibilities of bus contention can easily he recognized and avoided either by hardware or use of proper device locations in software. The technique is also a useful analysis tool