Title :
No clock, no bus - no sweat [asynchronous IC interconnect network]
Abstract :
This article presents a UK start-up which believes it has come up with a fundamental shift in interconnection technology that will solve timing closure problems in complex chips. It is based on an asynchronous design and uses packet switching technology. It is expected to be particularly effective in SoC design.
Keywords :
asynchronous circuits; integrated circuit interconnections; logic design; packet switching; system-on-chip; timing; IC interconnect network; SoC design; asynchronous design; chip timing closure problems; packet switching technology;
Journal_Title :
IEE Review
DOI :
10.1049/ir:20040901
