DocumentCode :
1151681
Title :
Layout Influences Testability
Author :
Spencer, Thomas H. ; Savir, Jacob
Author_Institution :
Stanford University
Issue :
3
fYear :
1985
fDate :
3/1/1985 12:00:00 AM
Firstpage :
287
Lastpage :
290
Abstract :
This correspondence addresses actual implementation of a multiway fan-out and its effect on test generation. If a test generation ignores the fan-out implementation faults may be left undetected by the test set. Moreover, different implementations of the multiway fan-out may lead to different fault coverages. Careless implementation of the fan-out may also yield undetectable faults. Some guidelines for fan-out implementation that may enhance testability are given in this correspondence.
Keywords :
Boolean difference; fan-out; layout; masking; reconvergent fan-out; Circuit faults; Circuit synthesis; Circuit testing; Data systems; Electrical fault detection; Fault detection; Guidelines; Jacobian matrices; Process design; Wires; Boolean difference; fan-out; layout; masking; reconvergent fan-out;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.1985.1676573
Filename :
1676573
Link To Document :
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