• DocumentCode
    1151770
  • Title

    Dynamically Restructurable Fault-Tolerant Processor Network Architectures

  • Author

    Pradhan, Dhiraj K.

  • Author_Institution
    Departnment of Electrical and Computer Engineering, University of Massachusetts
  • Issue
    5
  • fYear
    1985
  • fDate
    5/1/1985 12:00:00 AM
  • Firstpage
    434
  • Lastpage
    447
  • Abstract
    A class of novel fault-tolerant multiprocessor networks is proposed. These networks are restructurable in that they can assume different logical configurations to suit different problem environments. More importantly, this restructuriing capability is not altered even after the occurrence of faults. These networks are novel in that they uniquely combine certain desirable features, including self-routing of messages, dynamic reconfigurability, fault-tolerance, the ability to incorporate incremental extension, as well as the capacity to be partitioned with fault-tolerance. What is important about these fault-tolerant features is that they are built-in as an integral part of the design, and not as done traditionally, by means of redundancy.
  • Keywords
    Binary tree; circuit switching; distributed system; dynamic processing; emulation; faplt-tolerance; fault-tolerant interconnection; linear array; nmodular network; packet switching; parallel system; processor array; self-routing; Circuit faults; Computer architecture; DH-HEMTs; Fault tolerance; Integrated circuit interconnections; Packet switching; Redundancy; Robustness; Routing; Telecommunication network reliability; Binary tree; circuit switching; distributed system; dynamic processing; emulation; faplt-tolerance; fault-tolerant interconnection; linear array; nmodular network; packet switching; parallel system; processor array; self-routing;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.1985.1676583
  • Filename
    1676583