Integrated-Circuit Logarithmic Arithmetic Units

Author

Lang, Jeffrey H. ; Zukowski, Charles A. ; LaMaire, Richard O. ; Chae Han

Author_Institution

Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology

Issue

5

fYear

1985

fDate

5/1/1985 12:00:00 AM

Firstpage

475

Lastpage

483

Abstract

This correspondence examines integrated-circuit logarithmic arithmetic units which include adders, subtracters, multipliers, and dividers. The design of these arithmetic units is reviewed, and an example arithmetic unit which performs multiplication followed by addition is designed in detail. The design results are used to develop a size and speed comparison of integrated-circuit logarithmic and fixed-point arithmetic units. This comparison is exercised through a video signal processing example. It is concluded from this comparison that logarithmic arithmetic units are smaller than, and as fast as, fixed-point arithmetic units with comparable capabilities in digital signal processing applications characterized by large dynamic range and moderate computational accuracy requirements. Further, this comparison quantitatively illustrates the interaction of digital-signal-processing and integrated-circuit issues in the design of special-purpose digital signal processors.

Keywords

Arithmetic unit comparisons; VLSI; logarithmic arithmetic; multiplier-accumulators; special-purpose digital signal processors; Automatic control; Digital arithmetic; Digital signal processing; Digital signal processors; Dynamic range; Fixed-point arithmetic; Quantization; Signal design; Very large scale integration; Video signal processing; Arithmetic unit comparisons; VLSI; logarithmic arithmetic; multiplier-accumulators; special-purpose digital signal processors;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/TC.1985.1676588

Filename

1676588