DocumentCode
1152188
Title
A Symmetric Tree Structure Interconnection Network and its Message Traffic
Author
Woo, Nam Sung ; Agrawala, Ashok
Author_Institution
AT&T Bell Laboratories
Issue
8
fYear
1985
Firstpage
765
Lastpage
769
Abstract
A variation of the tree structure interconnection network for the message switching multiprocessor system is presented in this correspondence. It mainly consists of four binary tree structures, pairs of which are touched by their leaf nodes; in addition, there are four nodes which interface with external environments. The proposed network is left-right and top-down symmetric and is planar. Every node in the interconnection network has the same number of degree, 3. There are multiple paths between any two nodes in the network. Results of the message traffic analysis of the network are presented.
Keywords
Extended even-odd node numbering; interconnection network for VLSI implementation; message traffic analysis; top-down/left-right symmetric tree structure; Counting circuits; Digital systems; Hardware; Interference; Multiprocessor interconnection networks; Operating systems; Parallel programming; Seminars; Telecommunication traffic; Tree data structures; Extended even-odd node numbering; interconnection network for VLSI implementation; message traffic analysis; top-down/left-right symmetric tree structure;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.1985.1676626
Filename
1676626
Link To Document