Partitioned state encoding for low power in FPGAs

The problem of finite state machine (FSM) encoding for low power in field-programmable gate arrays (FPGAs) is addressed. In this technology, one-hot encoding is typically recommended for large FSMs and binary encoding for small FSMs. A partitioned encoding approach is proposed which uses a combination of both binary encoding and zero-one-hot encoding with intermediate code size. Experimental results demonstrate that the proposed encoding approach can produce significant power savings.