DocumentCode
1152420
Title
Lateral Trapped-Charge Profiling Based on the Extraction of the Flatband Voltage by Using the Optical Substrate Current in Nitride-Based Charge-Trap Flash Memories
Author
Roh, Kang-Seob ; Park, Sungwook ; Kim, Dae Hwan ; Kim, Dong Myong
Author_Institution
Sch. of Electr. Eng., Kookmin Univ., Seoul, South Korea
Volume
56
Issue
9
fYear
2009
Firstpage
2034
Lastpage
2044
Abstract
A lateral charge-profiling technique based on local-flatband-voltage (VFB)monitoring using optical-substrate-current spectroscopy (ISub, photo spectroscopy) in nitride-based charge-trap flash (CTF) memories is proposed. Under optical illumination by photons with above-bandgap energy Eph(>Eg,Si), ISub, photo is abruptly increased at the gate voltage VG=VFB due to a sudden increase of the excess minority-carrier diffusion current. As expected in this principle, while the single-step feature of the ISub, photo-VG curve is observed in the case of N-MOSFETs, a multistep response is clearly observed in nitride-based CTF memories. The mechanism of steplike ISub, photo spectroscopy is analyzed, supported by analytical models, and verified by comparison with TCAD simulation results. The results show that the height of the step corresponds to the lateral length LTC of the region, over which localized trapped charges are distributed, and its width to the density Qnit(x)=qNnit(x) [C/cm2] in the nitride storage layer. Based on the proposed ISub, photo spectroscopy, lateral charge profiling is demonstrated in a programmed NROM cell. The validity of the proposed ISub, photo spectroscopy is confirmed by comparing the measured ID-VG characteristics with TCAD simulation incorporating the extracted Nnit(x) by ISub, photo spectroscopy. The proposed lateral charge-profiling technique is expected to be a useful technique for extracting the trapped-charge distribution in NROM and/or multibit CTF memories. This extraction technique has advantages of electrical stress free, exclusion of the effect from interface traps, and the applicability to devices with large gate leakage current.
Keywords
MOSFET; carrier lifetime; circuit simulation; electron traps; flash memories; minority carriers; technology CAD (electronics); N-MOSFETs; TCAD simulation; above-bandgap energy; electrical stress; gate leakage current; lateral trapped-charge profiling; local-flatband-voltage monitoring; localized trapped charges; minority-carrier diffusion current; nitride storage layer; nitride-based charge-trap flash memories; optical photon illumination; optical-substrate-current spectroscopy; programmed NROM cell; Analytical models; Charge carrier processes; Flash memory; Leakage current; Lighting; MOSFET circuits; Monitoring; Spectroscopy; Stress; Voltage; Above-bandgap photon; MOSFET; channel hot-electron injection; charge-trap Flash (CTF) memory; flatband voltage; lateral charge profile; nonuniform charge trapping; optical-substrate-current spectroscopy; simulation;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2009.2026320
Filename
5175376
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