Title :
Built-In Testing of Memory Using an On-Chip Compact Testing Scheme
Author :
Kinoshita, Kozo ; Saluja, Kewal K.
Author_Institution :
Department of Information ahd Behavioral Sciences, Faculty of Integrated Arts and Sciences, Hiroshima University
Abstract :
In this paper we study the problem of testing RAM. A new fault model, which encompasses the existing fault models, is proposed. We then propose a scheme of testing faults from the new fault model using built-in testing techniques. We introduce concept of p-hard and determine the complexity of the extra hardware required for built-in self-testing on our hardness scale. A novel approach using microcoded ROM for implementation of built-in testing is also proposed and its complexity is determined.
Keywords :
Built-in self-testing (BIST); built-in testing (BIT); hardware complexity; pattern-sensitive faults; random- access memory (RAM); stuck-at faults; weight-sensitive faults; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Costs; Decoding; Fault detection; Hardware; Random access memory; Read-write memory; Built-in self-testing (BIST); built-in testing (BIT); hardware complexity; pattern-sensitive faults; random- access memory (RAM); stuck-at faults; weight-sensitive faults;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1986.1676677
