Author´s Reply

The paper by Schertz and Metze [1] is concerned with combinational circuits having a certain restricted fan-out structure. Two-level circuits have this restricted structure. A PLA as defined in [2] with only G and D faults behaves like a two-level combinational circuit with stuck-at faults. Hence, the results of Schertz and Metze are applicable. In an AND-OR PLA, a G fault is equivalent to a stuck-at-1 fault on an AND gate input, and a D fault is equivalent to a stuck-at-0 fault on an OR gate input. S and A faults are in a sense "duals" of G and D faults, and results concerning fault masking (and multiple-fault detection) for S and A faults in two-level circuits can be derived in a manner similar to G and D faults.