Abstract :
Network processors are programmable, highly integrated communications circuits optimized to provide processing at high data and packet rates. The packet instruction set computer (PISC) architecture is a synchronous dataflow architecture developed for network processors. It uses a deep pipeline that contains two types of processing elements: PISC processors, which perform programmable data manipulation, and I/O processors, which provide access to shared resources such as look-up table memory, hardware accelerators, or coprocessors.
Keywords :
data flow computing; multiprocessing systems; pipeline processing; reduced instruction set computing; resource allocation; synchronisation; I/O processor; PISC processor; coprocessor; hardware accelerator; integrated communications circuit; look-up table memory; network processor; packet instruction set computer architecture; programmable data manipulation; synchronous dataflow architecture; Application software; Circuit topology; Computer architecture; Network topology; Open systems; Parallel processing; Pipelines; Process design; Routing; Transport protocols;
