• DocumentCode
    1153022
  • Title

    NePSim: a network processor simulator with a power evaluation framework

  • Author

    Luo, Yan ; Yang, Jun ; Bhuyan, Laxmi N. ; Zhao, Li

  • Author_Institution
    Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA
  • Volume
    24
  • Issue
    5
  • fYear
    2004
  • Firstpage
    34
  • Lastpage
    44
  • Abstract
    This article presents NePSim, an integrated system that includes a cycle-accurate architecture simulator, an automatic formal verification engine, and a parameterizable power estimator for NPs consisting of clusters of multithreaded execution cores, memory controllers, I/O ports, packet buffers, and high-speed buses. To perform concrete simulation and provide reliable performance and power analysis, we defined our system to comply with Intel´s IXP1200 processor specification because academia has widely adopted it as a representative model for NP research.
  • Keywords
    computer architecture; computer networks; digital simulation; formal verification; low-power electronics; microprocessor chips; I/O port; Ivcri verification engine; NePSim; formal verification engine; memory controller; multithreaded execution core; network processor simulator; packet buffer; power evaluation; Computational modeling; Computer architecture; Engines; Open source software; Performance analysis; Power dissipation; Power system modeling; Power system reliability; Random access memory; SDRAM;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/MM.2004.52
  • Filename
    1353201