Title :
Multiple Stuck-Fault Detection and Location in Multivalued Linear Circuits
Author :
Chen, Chuen-Liang ; Du, Min-Wen
Author_Institution :
Department of Computer Science and Information Engineering, National Taiwan University
Abstract :
In this correspondence, we present procedures for constructing universal fault detection test sets as well as fault location test sets for multivalued linear circuits, under a multiple stuck-fault model. The bin packing problem is involved in the procedures. The sizes of the fault detection test set and the fault location test set constructed for an n- variable v-valued linear tree circuit are 1 + ⌈n/(v − 1)⌉ and 1 + ⌈n/ ⌊log2 v⌋ ⌉, respectively. It has been proved that the sizes listed above are optimal for some cases.
Keywords :
Bin packing problem; linear circuit; multivalued logic; stuck-fault detection/location; universal test set; Circuit faults; Circuit testing; Computer science; Electrical fault detection; Fault location; Linear circuits; Logic circuits; Logic testing; Multivalued logic; Vectors; Bin packing problem; linear circuit; multivalued logic; stuck-fault detection/location; universal test set;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1986.1676714