DocumentCode
1153122
Title
On the Scaling of Flash Cell Spacer for Gate Disturb and Charge Retention Optimization
Author
Lee, Yung-Huei ; McMahon, William ; Lu, Yin-Lung Ryan ; Tewg, Jun-Yen J. ; Ma, Sean T.
Author_Institution
California Technol. Center, Numonyx, Santa Clara, CA, USA
Volume
56
Issue
9
fYear
2009
Firstpage
1959
Lastpage
1965
Abstract
Self-aligned contact processes enable aggressive scaling of the cell sidewall spacer for advanced nor Flash technology. Spacer scaling can increase bake-induced charge loss/gain and gate disturb. High-quality spacer dielectrics are necessary to reduce the bake shift and gate disturb effects. The peak field at the floating gate corner, in particular, plays a significant role in gate disturb.
Keywords
dielectric materials; flash memories; floating point arithmetic; logic gates; optimisation; cell sidewall spacer; charge retention optimization; flash cell spacer scaling; floating gate corner; gate disturb; nor flash technology; self-aligned contact; spacer dielectrics; Capacitors; Chemical technology; Dielectric measurements; EPROM; Electrons; Nonvolatile memory; Research and development; Space technology; Testing; Threshold voltage; Cell scaling; charge retention; gate disturb; self-aligned contact (SAC) architecture; spacer oxide;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2009.2025912
Filename
5175443
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