DocumentCode
1153272
Title
A unified approach to reduce SOC test data volume, scan power and testing time
Author
Chandra, Anshuman ; Chakrabarty, Krishnendu
Author_Institution
Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
Volume
22
Issue
3
fYear
2003
fDate
3/1/2003 12:00:00 AM
Firstpage
352
Lastpage
363
Abstract
We present a test resource partitioning (TRP) technique that simultaneously reduces test data volume, test application time, and scan power. The proposed approach is based on the use of alternating run-length codes for test data compression. We present a formal analysis of the amount of data compression obtained using alternating run-length codes. We show that a careful mapping of the don´t-cares in precomputed test sets to 1´s and 0´s leads to significant savings in peak and average power, without requiring either a slower scan clock or blocking logic in the scan cells. We present a rigorous analysis to show that the proposed TRP technique reduces testing time compared to a conventional scan-based scheme. We also improve upon prior work on run-length coding by showing that test sets that minimize switching activity during scan shifting can be more efficiently compressed using alternating run-length codes. Experimental results for the larger ISCAS89 benchmarks and an IBM production circuit show that reduced test data volume, test application time, and low power-scan testing can indeed be achieved in all cases.
Keywords
automatic test pattern generation; data compression; integrated circuit testing; logic testing; runlength codes; system-on-chip; ATPG; SoC test; alternating run-length codes; embedded core testing; formal analysis; scan power reduction; scan shifting; scan testing; switching activity; system-on-a-chip testing; test application time reduction; test data compression; test data volume reduction; test resource partitioning technique; unified approach; Automatic testing; Benchmark testing; Circuit testing; Clocks; Data compression; Energy consumption; Logic testing; System testing; System-on-a-chip; Test data compression;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2002.807895
Filename
1182080
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