(N, K) Concept Fault Tolerance

This paper describes a new fault-tolerant computer architecture based on a "distributed implementation" of a symbol- error correcting code. In this, as at is called, (N, K) concept the faults are masked by this code. The (N, K) concept is described in detail for N = 4 and K = 2. It is shown that symbol-error correcting codes having additional bit-error correcting capabilities make additional memory protection by means of bit-error correcting codes superfluous and a newly designed symbol-and bit- error correcting code for the