Title :
An Alternative to Scan Design Methods for Sequential Machines
Author :
Saluja, Kewal K. ; Dandapani, Ramaswami
Author_Institution :
Department of Electrical and Computer Engineering, University of Wisconsin
fDate :
4/1/1986 12:00:00 AM
Abstract :
The problem of testing sequential machines using a checking experiment is investigated. An algorithm is given to augment sequential machines by adding extra input(s) to make them testable. We also present a circuit modification method, similar to scan methods, such that the augmented machine can be tested by the checking experiment. A justification of our method for a VLSI environment is given by determining the overheads.
Keywords :
Built-in self test; checking experiments; scan design; sequential machines; testable design; Automatic testing; Circuit faults; Circuit testing; Clocks; Design methodology; Digital circuits; Hardware; Sequential analysis; Sequential circuits; Very large scale integration; Built-in self test; checking experiments; scan design; sequential machines; testable design;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1986.1676776
