Title :
A Study of Pipelining in Computing Arrays
Author :
Jagadish, Hosagrahar V. ; Mathews, Rob G. ; Kailath, Thomas ; Newkirk, John A.
fDate :
5/1/1986 12:00:00 AM
Abstract :
In this paper, we take a hard look at scheduling considerations in computing arrays. A simple sufficient condition is developed for determining whether a computing array can be pipelined. If the array cannot be pipelined in the form given, the condition also indicates the direction in which to proceed to make it pipelineable. The overall framework and methodology take a good part of the load off the logical architect of the array, and make the translation from the logical to the physical architecture a mechanical process.
Keywords :
Pipelining; systolic array; Circuits; Information systems; Laboratories; Logic arrays; Pipeline processing; Processor scheduling; Sufficient conditions; Systolic arrays; Throughput; Very large scale integration; Pipelining; systolic array;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1986.1676785