DocumentCode :
1153812
Title :
Minimization by the D Algorithm
Author :
Roth, J. Paul
Author_Institution :
IBM Thomas J. Watson Research Center
Issue :
5
fYear :
1986
fDate :
5/1/1986 12:00:00 AM
Firstpage :
476
Lastpage :
478
Abstract :
Programmed logic arrays [1], [2] are common in computer design. A form of this method of design has been used since the beginnings of computers, in telephone relay networks [3]. Optimization of such realizations of functions were begun by Karnaugh [4], Quine [5], McCluskey [6], and Roth [7]. Substantial use was mnade of such programs by Preiss [8] and Perlman [9]. Despite the existence of exact procedures, "fast," "approximate" procedures have been widely used. A new approximate procedure, using the D algorithm [1], [10], [11] is introduced here. It gets around a large computation, in complementation, using prior methods. Running programs "verify" this expectation.
Keywords :
D algorithm; PLA; logic; minimization; Computer networks; Costs; Design methodology; Input variables; Logic arrays; Logic design; Logic devices; Minimization methods; Programmable logic arrays; Software algorithms; D algorithm; PLA; logic; minimization;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.1986.1676790
Filename :
1676790
Link To Document :
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