Abstract :
A new pipeline architecture that combines the radix<2 and traditional 1.5 bit gain-stages is presented. The 10 bit, 60 MHz, 3 V pipelined analogue-to-digital converter has been designed in a 0.25 μm 1p4M CMOS technology using digital self-calibration. The converter achieves more than 57 dB SNDR from a 3 V supply (10% lower than nominal 3.3 V) within -40 to +120°C temperature range.
