• DocumentCode
    1153824
  • Title

    Combined radix<2 and 1.5 bit/stage pipelined analogue-to-digital converter

  • Author

    Nejati, B. ; Shoaei, O.

  • Volume
    39
  • Issue
    1
  • fYear
    2003
  • Firstpage
    2
  • Lastpage
    4
  • Abstract
    A new pipeline architecture that combines the radix<2 and traditional 1.5 bit gain-stages is presented. The 10 bit, 60 MHz, 3 V pipelined analogue-to-digital converter has been designed in a 0.25 μm 1p4M CMOS technology using digital self-calibration. The converter achieves more than 57 dB SNDR from a 3 V supply (10% lower than nominal 3.3 V) within -40 to +120°C temperature range.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; calibration; pipeline processing; -40 to 120 degC; 0.25 micron; 1.5 bit/stage; 10 bit; 3 V; 60 MHz; CMOS technology; SNDR; digital self-calibration; pipelined analogue-to-digital converter; radix<2 architecture;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20030070
  • Filename
    1182313
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1153824