Title :
An open-loop clock deskewing circuit for high-speed synchronous DRAM
Author_Institution :
DRAM Design Team, Samsung Electron., Hwa-Sung, South Korea
Abstract :
An open-loop clock deskewing circuit (CDC) for high-speed synchronous DRAM is described. Unlike the conventional circuits, the CDC does not require an additional measure delay line, thus power consumption is reduced. The delay is measured directly from the main delay line and both the input and output ports of the delay line are movable. The CDC provides a deskewed clock within two clock cycles.
Keywords :
DRAM chips; clocks; delay lines; high-speed integrated circuits; low-power electronics; CDC; clock cycles; delay line; high-speed synchronous DRAM; open-loop clock deskewing circuit; power consumption;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20030077
