Title :
RNS-based implementation of 8 × 8 point 2D-DCT over field-programmable devices [image compression]
Author :
Fernández, P.G. ; Lloris, A.
Author_Institution :
Departamento de Electronica y Tecnologia de Cornputadores, Campus Universitario Fuentenueva, Granada, Spain
Abstract :
A new implementation of an 8 × 8 two-dimensional discrete cosine transform (2D-DCT) processor based on the residue number system (RNS) is presented. This architecture makes use of a fast cosine transform algorithm. It is shown that the RNS implementation of the 2D-DCT over field-programmable logic devices leads to a 129% throughput improvement over the equivalent binary system.
Keywords :
data compression; discrete cosine transforms; field programmable gate arrays; image coding; pipeline arithmetic; residue number systems; 2D-DCT; RNS-based implementation; coding efficiency; fast cosine transform algorithm; field-programmable devices; field-programmable logic devices; image compression; pipelined architecture; two-dimensional discrete cosine transform;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20030084
