Reduced in-lock error DLL-based clock synthesiser with novel charge pump phase comparator

A reduced in-lock error and low jitter delay-locked loop (DLL)-based clock synthesiser employing a novel phase comparator and charge pump is proposed. HSPICE simulation results show the performance of this DLL-based synthesiser to be significantly better than that of other reported circuits. In particular, it has smaller in-lock error and lower output jitter.