• DocumentCode
    1154154
  • Title

    METRO-3D: an efficient three-dimensional wafer inspection simulator for next-generation lithography

  • Author

    Zhu, Zhengrong ; Swecker, Aaron L. ; Strojwas, Andrzej J.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
  • Volume
    17
  • Issue
    4
  • fYear
    2004
  • Firstpage
    619
  • Lastpage
    628
  • Abstract
    Wafer inspection schemes for next-generation lithography (NGL) will play a key role in controlling defect mechanisms and maintaining an acceptable yield. Developing these wafer inspection schemes will require characterization and optimization of deep ultraviolet (DUV) wavelength illumination at high numerical apertures (greater than 0.9) to detect defects that may be a fraction of the design rule. Using wafer inspection test benches that provide the flexibility for various illumination polarizations, numerical apertures, scanning, or full-field schemes can be extremely costly; therefore, simulation of these schemes is necessary to characterize the various detection parameters. To model defects for NGL, three-dimensional (3-D) simulation tools will be required to simulate highly absorptive material in the environment of shorter wavelength illumination. Also, the simulator will be required to simulate high numerical aperture (NA) inspection schemes to capture small defects. With the development of METRO-3D, a 3-D simulation tool that rigorously solves the EM field on arbitrary wafer topographies, we are able to model and characterize the wafer inspection schemes for NGL. We will present simulation results from METRO-3D for various wafer inspection schemes, including high NA schemes, on NGL topographies with highly absorptive materials.
  • Keywords
    inspection; integrated circuit manufacture; permittivity; ultraviolet lithography; 3D simulation tool; deep ultraviolet wavelength illumination; defect mechanisms control; next-generation lithography; shorter wavelength illumination; three dimensional wafer inspection; three-dimensional simulation tools; wafer topography; Apertures; Design optimization; Inspection; Lighting; Lithography; Numerical simulation; Polarization; Semiconductor device modeling; Surfaces; Testing; 65; Lithography; metrology; simulation;
  • fLanguage
    English
  • Journal_Title
    Semiconductor Manufacturing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0894-6507
  • Type

    jour

  • DOI
    10.1109/TSM.2004.835719
  • Filename
    1353319