Application-specific worst case corners using response surfaces and statistical models

Integrated circuits (ICs) must be robust to manufacturing variations. Circuit simulation at a set of worst case corners is a computationally efficient method for verifying the robustness of a design. This paper presents a new statistical methodology to determine the worst case corners for a set of circuit performances. The proposed methodology first estimates response surfaces for circuit performances as quadratic functions of the process parameters with known statistical distributions. These response surfaces are then used to extract the worst case corners in the process parameter space as the points where the circuit performances are at their minimum/maximum values corresponding to a specified tolerance level. Corners in the process parameter space close to each other are clustered to reduce their number, which reduces the number of simulations required for design verification. The novel concept of a relaxation coefficient to ensure that the corners capture the minimum/maximum values of all the circuit performances at the desired tolerance level is also introduced. The corners are realistic since they are derived from the multivariate statistical distribution of the process parameters at the desired tolerance level. The methodology is demonstrated with examples showing extraction of corners from digital standard cells and also the corners for analog/radio frequency (RF) blocks found in typical communication ICs.