Associative IC memories with relational search and nearest-match capabilities

Author

Jalaleddine, Sateh M S ; Johnson, Louis G.

Author_Institution

Dept. of Electr. Eng., Western Michigan Univ., Kalamazoo, MI, USA

Volume

27

Issue

6

fYear

1992

fDate

6/1/1992 12:00:00 AM

Firstpage

892

Lastpage

900

Abstract

The authors present the design and implementation of content addressable memories (CAMs) that execute relational and nearest-match instructions. Implementation of a novel relational search cell is presented. Direct performance comparison shows an order-of-magnitude improvement over existing designs with similar cell area. The design and implementation of a neural-inspired nearest-match CAM using a winner-take-all (WTA) network is presented. An original approach to analyzing such neural-inspired CAMs is presented. A model which describes the behavior of the WTA network is derived to be utilized in the design and performance prediction of the network. Performance of the WTA network in differentiating between words with large bit mismatches is analyzed, and an upper bound is set. Fully functional prototype chips have been fabricated through MOSIS using 2-μm double-metal CMOS technology. Theoretical, simulation, and physical chip measurements are in good agreement

Keywords

CMOS integrated circuits; content-addressable storage; integrated memory circuits; neural nets; 2 micron; MOSIS; associative IC memories; content addressable memories; double-metal CMOS technology; model; nearest-match instructions; neural-inspired nearest-match CAM; performance prediction; relational search cell; winner-take-all network; Associative memory; CADCAM; CMOS technology; Cams; Computer aided manufacturing; Performance analysis; Predictive models; Prototypes; Semiconductor device measurement; Upper bound;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.135333

Filename

135333