Title :
A 3.5-GHz PLL for fast low-IF/zero-IF LO switching in an 802.11 transceiver
Author :
Gierkink, Sander L J ; Li, Dandan ; Frye, Robert C. ; Boccuzzi, Vito
Author_Institution :
Agere Syst., Allentown, PA, USA
Abstract :
A PLL technique is introduced that enables fast and accurate frequency switching, independent of the loop bandwidth. It uses separate tuning paths, each driving a separate VCO tune port. Different frequencies are produced by letting the VCO make different weighted combinations of the stable tuning voltages. The PLL converges to the stable tuning voltages by switching it a few times between the desired frequencies and tuning paths. Once the stabilized tuning voltages are found, one can switch between frequencies as fast as one can switch between KVCOs. The technique is applied to a 3.5-GHz integer-N PLL to enable fast jumping of the local oscillator (LO) frequency when an 802.11 transceiver is switched between a low and a zero intermediate frequency (LIF/ZIF). It uses dual phase/frequency detectors (PFD), charge pumps (CPs), and on-chip loop filters to control two separate low-leakage VCO tune ports. Each PFD/tune port combination can be (de)activated separately, without disturbing the loop filters´ charge. The 50-kHz bandwidth PLL achieves a measured 7-MHz jump with ±20 kHz accuracy within 6 μs. The measured phase noise is -123 dBc/Hz at 1-MHz offset.
Keywords :
IEEE standards; circuit tuning; phase locked loops; switching; transceivers; voltage-controlled oscillators; 3.5 GHz; 50 KHz; 6 mus; 802.11 transceiver; PLL; VCO; charge pumps; fast low-IF/zero-IF LO switching; frequency switching; frequency synthesizers; local oscillator frequency; loop bandwidth; on-chip loop filters; phase noise; phase-locked loops; phase/frequency detectors; voltage-controlled oscillators; Bandwidth; Filters; Local oscillators; Phase frequency detector; Phase locked loops; Switches; Transceivers; Tuning; Voltage; Voltage-controlled oscillators; Frequency synthesizers; phase-locked loops; voltage-controlled oscillators;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2005.848175