A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization

Author

Balan, Vishnu ; Caroselli, Joe ; Chern, Jenn-Gang ; Chow, Catherine ; Dadi, Ratnakar ; Desai, Chintan ; Fang, Leo ; Hsu, David ; Joshi, Pankaj ; Kimura, Hiroshi ; Liu, Cathy Ye ; Pan, Tzu-Wang ; Park, Ryan ; You, Cindy ; Zeng, Yi ; Zhang, Eric ; Zhong, Fr

Author_Institution

Commun. & ASIC Technol. Dept., LSI Logic Corp., Milpitas, CA, USA

Volume

40

Issue

9

fYear

2005

Firstpage

1957

Lastpage

1967

Abstract

In this paper, a serial link design that is capable of 4.8-6.4-Gb/s binary NRZ signaling across 40´´ of FR4 copper backplane traces and two connectors is described. The transmitter features a programmable two-tap feed forward equalizer and the receiver uses an adaptive four-tap decision feedback equalization to compensate for the losses in the channel at 6.4 Gbps. The transceiver core is built in LSI´s 0.13-μm standard CMOS technology to be integrated into ASIC designs that require serial links. The transceiver consumes 310 mW per duplex channel at 1.2 V and 6.4 Gb/s under nominal conditions.

Keywords

CMOS digital integrated circuits; adaptive equalisers; application specific integrated circuits; decision feedback equalisers; 0.13 micron; 1.2 V; 310 mW; 4.8 to 6.4 Gbit/s; 40 in; ASIC; CMOS technology; NRZ signaling; adaptive four tap decision feedback equalization; backplane; programmable two tap feed forward equalizer; serial link; Backplanes; CMOS technology; Connectors; Copper; Decision feedback equalizers; Feeds; Optical signal processing; Signal design; Transceivers; Transmitters; Adaptive equalization; SerDes; backplane transceiver; decision feedback equalization (DFE); serial link;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2005.848180

Filename

1501996