DocumentCode
1155266
Title
A design of programmable logic arrays with random pattern-testability
Author
Fujiwara, Hideo
Author_Institution
Dept. of Electron. & Commun., Meiji Univ., Kawasaki, Japan
Volume
7
Issue
1
fYear
1988
fDate
1/1/1988 12:00:00 AM
Firstpage
5
Lastpage
10
Abstract
A testable design of programmable logic arrays (PLAs) with high fault coverage for random test patterns is introduced. Low area overhead is achieved by adding a mask array between the input-decoder and the AND array of the PLA. Several variations of the proposed approach are presented. The probability of fault detection and the test length are examined for both stuck-type and crosspoint-type faults to estimate the fault coverage achievable with the random patterns
Keywords
cellular arrays; integrated logic circuits; logic design; logic testing; AND array; PLAs; crosspoint-type faults; fault coverage; fault detection; input-decoder; mask array; programmable logic arrays; random pattern-testability; random test patterns; stuck-type; test length; testable design; Built-in self-test; Circuit faults; Circuit testing; Fault detection; Logic arrays; Logic design; Logic testing; Programmable logic arrays; Sequential analysis; Software testing;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.3125
Filename
3125
Link To Document