A digital signal processor for an ANSI standard ISDN transceiver

Author

Agazzi, Oscar E. ; Koh, Taiho ; Haider, Syed S. ; Walden, Robert W. ; Cassiday, Daniel R. ; Wilson, Gene A. ; Lalumia, T. Mariano ; Gerveshi, Christine M. ; Kumar, Jitendra ; Crochiere, Ronald E. ; Shaw, Robert F. ; Wilson, Ralph A. ; McDonald, William R.

Author_Institution

AT&T Bell Lab., Murray Hill, NJ, USA

Volume

24

Issue

6

fYear

1989

fDate

12/1/1989 12:00:00 AM

Firstpage

1605

Lastpage

1613

Abstract

The digital signal processing chip of a two-chip ISDN (integrated services digital network) basic access transceiver based on the ANSI standard 2B1Q code is described. Nonlinear echo cancellation is used to improve the loop coverage. The chip features a multiprocessor architecture, where each processor is optimized for the algorithm used. Full observability of internal signals and adaptive filter coefficients is supported. The device is fabricated in a 1.25-μm double-level-metal CMOS process with an active area of 47 mm²

Keywords

CMOS integrated circuits; ISDN; computerised signal processing; data communication equipment; digital signal processing chips; echo suppression; multiprocessing systems; standards; telecommunications computing; transceivers; 1.25 micron; 2B1Q code; ANSI standard; DSP chip; ISDN transceiver; adaptive filter coefficients; digital signal processor; double-level-metal CMOS process; integrated services digital network; multiprocessor architecture; nonlinear echo cancellation; two chip basic access transceiver; ANSI standards; Adaptive filters; CMOS process; Digital signal processing chips; Digital signal processors; Echo cancellers; ISDN; Observability; Signal processing algorithms; Transceivers;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.44996

Filename

44996