Title :
An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-μm CMOS
Author :
Stonick, John T. ; Wei, Gu-Yeon ; Sonntag, Jeff L. ; Weinlader, Daniel K.
Author_Institution :
Accelerant Networks Inc., Beaverton, OR, USA
fDate :
3/1/2003 12:00:00 AM
Abstract :
This paper describes a backplane transceiver, which uses pulse amplitude modulated four-level (PAM-4) signaling and continuously adaptive transmit-based equalization to move 2.5-GBd/s symbols totalling 5 Gb/s across typical FR-4 backplanes for total distances of up to 50 inches through two sets of backplane connectors. The 17-mm2 device is implemented in a 0.25-μm CMOS process, operates off of 2.5- and 3.3-V supply voltages, and consumes 1 W.
Keywords :
CMOS integrated circuits; adaptive equalisers; pulse amplitude modulation; telecommunication signalling; transceivers; 0.25 micron; 1 W; 2.5 V; 3.3 V; 5 Gbit/s; CMOS process; PAM-4; adaptive equalization; backplane transceiver; four-level signaling; pulse amplitude modulation; Adaptive equalizers; Amplitude modulation; Backplanes; Circuits; Clocks; Connectors; Dielectric losses; Frequency synthesizers; Pulse modulation; Transceivers;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2002.808282
