Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era

Several physical phenomena in highly scaled CMOS technology have now become first-order elements affecting the electrical behavior of transistor characteristics. Effects such as STI mechanical stress, direct tunneling in gate dielectrics, gate line-edge roughness, and others can have significant influence on device characteristics. This paper elaborates on these effects to exemplify the need for closer interaction between circuit design and process development teams in order to push out application-dependent scaling limits. The paper also highlights the need for further efforts in the areas of circuit-level device modeling.