DocumentCode :
1157931
Title :
COSMOS-a novel MOS device paradigm
Author :
Kaya, Savas
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Ohio Univ., Athens, OH, USA
Volume :
4
Issue :
5
fYear :
2005
Firstpage :
588
Lastpage :
593
Abstract :
Downscaling alone is not sufficient to sustain the development of CMOS devices, and further paradigm shifts are necessary. In this paper, we argue such a shift is possible and show through technology computer-aided design simulations that a symmetrically operating CMOS device pair may be built under a single gate structure by a surprisingly simple choice of device layout and channel engineering parameters. As a result, we predict that another seemingly fundamental CMOS architectural requirement, the need to build two separate MOSFETs with individual gate stacks, may be eliminated. We call this new architecture a complementary orthogonal stacked MOS (COSMOS), which places the n and p MOSFETs perpendicular to one another under a single gate, integrating them vertically, as well as laterally. We demonstrate how the device may be built, operated, and optimized for symmetric operation, as well as verifying logic NOT operation via three-dimensional device simulations. The COSMOS architecture would not only mean significant savings in the active device area of a conventional digital CMOS layout, but also reductions in RC device parasitics associated with building and wiring two sets of devices for a single Boolean output function.
Keywords :
Boolean functions; CMOS integrated circuits; Ge-Si alloys; MOSFET; field effect transistors; leakage currents; logic CAD; logic gates; silicon-on-insulator; 3D device simulations; Boolean output function; CMOS devices; CMOS field-effect transistors; CMOS integrated circuits; COSMOS architecture; MOSFET devices; RC device; Si-Ge; active device area; complementary orthogonal stacked MOS device; computer-aided design simulations; conventional digital CMOS layout; leakage currents; logic NOT operation; paradigm shifts; silicon-germanium alloys; silicon-on-insulator technology; ultra-large-scale integration; Buildings; CMOS logic circuits; CMOS technology; Computational modeling; Computer simulation; Design automation; Design engineering; Logic devices; MOS devices; MOSFETs; CMOS field-effect transistors (FETs); CMOS integrated circuits (ICs); leakage currents; silicon–germanium alloys; silicon-on-insulator (SOI) technology; ultra-large-scale integration;
fLanguage :
English
Journal_Title :
Nanotechnology, IEEE Transactions on
Publisher :
ieee
ISSN :
1536-125X
Type :
jour
DOI :
10.1109/TNANO.2005.851423
Filename :
1504718
Link To Document :
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