• DocumentCode
    1158454
  • Title

    Force-Directed Methods for Generic Placement

  • Author

    Kennings, Andrew ; Vorwerk, Kristofer P.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont.
  • Volume
    25
  • Issue
    10
  • fYear
    2006
  • Firstpage
    2076
  • Lastpage
    2087
  • Abstract
    This paper describes the implementation of a wire length-driven force-directed placer named FDP for generic placement. Specifically, it describes efficient force computation for cell spreading, numerical instabilities during force-directed placement, a means to avoid instabilities, and metrics for proper assessment of cell distribution throughout the placement region. It demonstrates that one of the greatest impediments to achieving high-quality placements using a force-directed placer lies in the large amount of cell overlap present in initial placements. This overlap makes the determination of cell ordering difficult and can lead to the inadvertent separation of highly connected cells. It is shown that median improvement and multilevel clustering improve cell ordering and aid in wire length minimization. Numerical results are presented for both standard cell and mixed-size placement problems. For standard cell problems, the tool generates placements that are, on average, 3% better than Capo9.0, but 5% worse than FengShui2.6. For mixed-size problems, FDP generated placements that are, on average, 2%-5% better than Capo9.0 and -5%--2% better than Fengshui2.6, depending on the presence (or absence) of pin offsets. Run times for FDP are higher than both Capo9.0 and FengShu2.6, although reasonable
  • Keywords
    integrated circuit layout; cell distribution; cell ordering; cell spreading; force-directed methods; force-directed placer; generic placement; median improvement; mixed-size placement problems; multilevel clustering; standard cell placement problems; wire length minimization; Automation; Circuit simulation; Distributed computing; Impedance; Integrated circuit layout; Minimization; Optimization methods; Simulated annealing; Very large scale integration; Wire; Design automation; force-directed placement; integrated circuit layout; quadratic placement;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2005.862748
  • Filename
    1677692