Title :
Statistical Analysis and Design of HARP FPGAs
Author :
Wang, Gang ; Sivaswamy, Satish ; Ababei, Cristinel ; Bazargan, Kia ; Kastner, Ryan ; Bozorgzadeh, Elaheh
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA
Abstract :
Modern field programmable gate array (FPGA) architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configurations. However, providing such a great flexibility comes at a high cost in terms of area, delay, and power. The authors propose a new FPGA routing architecture that utilizes a mixture of hardwired and traditional flexible switches. The result is an about a 30% reduction in leakage power consumption, a 5% smaller area, and 20% shorter delays, which translates to a 25% increase in the clock frequency. Despite the increase in clock speeds, the overall power consumption is reduced
Keywords :
field programmable gate arrays; integrated circuit design; logic design; statistical analysis; FPGA routing architecture; HARP FPGA design; field programmable gate array architectures; leakage power consumption; statistical analysis; Application specific integrated circuits; Clocks; Costs; Delay; Energy consumption; Field programmable gate arrays; Routing; Statistical analysis; Switches; Switching circuits; Architecture; field programmable gate arrays; integrated circuits; routing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2005.859485
