Title :
A power efficient differential 20-GHz low noise amplifier with 5.3-GHz 3-dB bandwidth
Author :
Guo, Xiaoling ; O, K.K.
Author_Institution :
Silicon Microwave Integrated Circuits & Syst. Res. Group, Univ. of Florida, Gainesville, FL, USA
Abstract :
A 20-GHz differential two-stage low-noise amplifier (LNA) is demonstrated in a foundry digital 130-nm CMOS technology with 8-metal layers. This LNA has 20-dB voltage gain and ∼5.5-dB noise figure at 20GHz with 24-mW power consumption. The measured IP1 dB and IIP3 are -11 dBm and -4dBm. Compared to the previously published bulk CMOS LNAs operating above 20GHz, this LNA has exceptionally low power and current consumption especially considering its differential topology and wide bandwidth.
Keywords :
CMOS digital integrated circuits; MMIC amplifiers; differential amplifiers; 130 nm; 20 GHz; 20 dB; 24 mW; 5.3 GHz; 5.5 dB; differential topology; digital CMOS technology; low current consumption; low noise amplifier; low power consumption; metal layers; noise figure; power efficient differential amplifier; voltage gain; wide bandwidth; Bandwidth; CMOS technology; Differential amplifiers; Energy consumption; Impedance matching; Low-noise amplifiers; Parasitic capacitance; Radio frequency; Radiofrequency amplifiers; Voltage; 130nm CMOS; Low-noise amplifier (LNA);
Journal_Title :
Microwave and Wireless Components Letters, IEEE
DOI :
10.1109/LMWC.2005.855383
