A front-end processor for modems

Author

Yamamoto, Kazushige ; Yanaga, Osamu ; Okuaki, Yasuyuki

Author_Institution

OKI Electr. Ind. Co. Ltd., Tokyo, Japan

Volume

24

Issue

6

fYear

1989

fDate

12/1/1989 12:00:00 AM

Firstpage

1634

Lastpage

1638

Abstract

A front-end processor constructed of an oversampling delta-sigma ADC/DAC (analog-to-digital converter/digital-to-analog converter) and a digital signal processor is described. The chip can handle a maximum of eight different processing modes for modem applications including the echo canceling scheme. The chip incorporates a voltage reference circuit, digital PLL (phase-locked loop), and a unique second interpolation circuit to realize both conventional QAM (quadrature amplitude modulation) demodulation and echo cancel-type demodulation. The chip is fabricated in a 1.5-μm double-poly double-metal CMOS process. The chip size is 9.2 mm×7.2 mm, and the typical power consumption is 150 mW with a single +5.0-V power supply

Keywords

CMOS integrated circuits; analogue-digital conversion; digital signal processing chips; digital-analogue conversion; echo suppression; modems; 1.5 micron; 150 mW; 5 V; A/D convertor; CMOS process; D/A convertor; QAM demodulation; digital PLL; digital signal processor; double-poly double-metal; echo cancel-type demodulation; echo canceling scheme; front-end processor; interpolation circuit; modems; multistandard type; oversampling delta-sigma ADC/DAC; phase-locked loop; power consumption; quadrature amplitude modulation; single +5.0-V power supply; voltage reference circuit; Analog-digital conversion; Circuits; Demodulation; Digital signal processors; Digital-analog conversion; Interpolation; Modems; Phase locked loops; Quadrature amplitude modulation; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.44999

Filename

44999