A gate-charging model for ILD related plasma processes in MOSFETs

Author

Lin, Wallace ; Sery, George

Author_Institution

Intel Corp., Santa Clara, CA, USA

Volume

24

Issue

1

fYear

2003

Firstpage

10

Lastpage

12

Abstract

A model explaining gate-charging damage in MOSFETs observed during inter-layer-dielectric (ILD)-related plasma processes is reported. It indicates that the charging damage associated with the ILD plasma process can be related to the effect of photoconduction and/or capacitive impedance coupling of plasma potential through the multiple ILD layers. The model leads to a conclusion that by placing a larger-area lower-layer metal (such as Metal-1) plate or polysilicon plate at the gate terminal of MOSFETs, this ILD process-related charging damage can be eliminated or significantly reduced due to a substantial reduction in the gate-to-substrate impedance of the transistors.

Keywords

MOSFET; dielectric thin films; plasma materials processing; semiconductor device models; semiconductor process modelling; surface charging; ILD related plasma processes; MOSFETs; N-MOSFET test structures; capacitive impedance coupling; charging damage; five-metal-layer CMOS technology; gate terminal; gate-charging model; gate-to-substrate impedance reduction; inter-layer-dielectric; larger-area lower-layer metal plate; photoconduction; plasma potential; polysilicon plate; CMOS technology; Etching; Impedance; Integrated circuit modeling; MOSFET circuits; Photoconductivity; Plasma applications; Protection; Semiconductor device modeling; Testing;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2002.807022

Filename

1185194