DocumentCode :
1159913
Title :
Netlisting and Modeling Well-Proximity Effects
Author :
Watts, Josef ; Su, Ke-Wei ; Basel, Mark
Author_Institution :
Semicond. Res. & Dev. Center, IBM Corp., Essex Junction, VT
Volume :
53
Issue :
9
fYear :
2006
Firstpage :
2179
Lastpage :
2186
Abstract :
In advanced CMOS technologies, transistor characteristics depend not only on the layout of the device itself but also on the layout of the adjacent structures. For the compact model to accurately predict circuit behavior, it needs information about the transistor and the structures surrounding it. For the simulator to efficiently handle a large number of transistors, the information about the surrounding layout must be reduced to a small number of parameters for each transistor instance. The parameters must be such that they can be efficiently calculated from the layout by the layout-versus-schematic tool. This paper describes the solution chosen by the Government Electronics and Information Technology Association Compact Model Council for modeling the effect of well edges near a transistor and proposes general guidelines for efficient solutions for modeling other proximity layout effects
Keywords :
CMOS integrated circuits; integrated circuit layout; integrated circuit modelling; proximity effect (lithography); CMOS technologies; circuit behavior; layout device; netlisting; transistor characteristics; well proximity effects; CMOS technology; FETs; Implants; Integrated circuit layout; Integrated circuit modeling; MOSFETs; Predictive models; Resists; Semiconductor device modeling; Transistors; Integrated circuit ion implantation; MOSFETs; integrated circuit layout; integrated circuit modeling;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2006.880176
Filename :
1677851
Link To Document :
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