Reliability Comparison of Triple-Gate Versus Planar SOI FETs

Author

Crupi, Felice ; Kaczer, Ben ; Degraeve, Robin ; Subramanian, Vaidy ; Srinivasan, Purushothaman ; Simoen, Eddy ; Dixit, Abhisek ; Jurczak, Malgorzata ; Groeseneken, Guido

Author_Institution

Dipt. di Elettronica, Univ. della Calabria, Rende

Volume

53

Issue

9

fYear

2006

Firstpage

2351

Lastpage

2357

Abstract

A comparative study of the reliability issues of triple-gate and planar FETs processed on the same silicon-on-insulator wafer is presented. It is shown that the triple-gate architecture does not alter the behavior of the time-dependent dielectric breakdown (BD) for different gate voltages and temperatures. The apparent higher Weibull slope observed in planar devices with respect to the triple-gate devices is ascribed to the area dependence of the time-to-BD detection. In spite of the different surface orientations, low-frequency noise measurements indicate similar values of the interface trap density for triple-gate and planar FETs

Keywords

CMOS integrated circuits; MOSFET; avalanche breakdown; integrated circuit reliability; silicon-on-insulator; CMOS reliability; Weibull slope; interface trap density; low-frequency noise measurements; planar SOI FET; reliability comparison; silicon-on-insulator wafer; time-dependent dielectric breakdown; triple-gate MOSFET; triple-gate SOI FET; CMOS technology; Dielectric breakdown; Dielectric substrates; FETs; FinFETs; Microelectronics; Scanning electron microscopy; Silicon on insulator technology; Temperature; Transmission electron microscopy; CMOS reliability; dielectrics breakdown (BD); silicon-on-insulator (SOI); triple-gate MOSFET;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2006.880824

Filename

1677874