Title :
An acoustic echo canceler
Author :
Hsu, Wenbin ; Chui, Frank ; Hodges, David A.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fDate :
12/1/1989 12:00:00 AM
Abstract :
The authors describe an experimental 1000-tap single-chip adaptive AEC (acoustic echo canceler) occupying 28 mm2 of die area in 3-μm, double-metal, p-well, CMOS technology. A floating-point format and power-of-two multiplications are chosen to simplify the hardware. To exploit pipelining and parallelism, interleaved data storage and multibank memory sharing the same addresses are designed. Hardware minimization is considered from both the system and the architecture perspective. In a loudspeaker telephone application, 27 dB of echo reduction is achieved after 1 s of convergence time
Keywords :
CMOS integrated circuits; computerised signal processing; digital signal processing chips; echo suppression; parallel architectures; pipeline processing; telecommunications computing; telephone equipment; 1000 tap configuration; 3 micron; CMOS technology; acoustic echo canceler; adaptive canceller chip; architecture; double-metal; floating-point format; interleaved data storage; loudspeaker telephone application; multibank memory sharing; p-well; parallelism; pipelining; power-of-two multiplications; single-chip; Acoustic devices; CMOS technology; Dynamic range; Feedback; ISDN; Laboratories; Loudspeakers; Microphones; Telephony; Wire;
Journal_Title :
Solid-State Circuits, IEEE Journal of
