Title :
A digital architecture employing stochasticism for the simulation of Hopfield neural nets
Author :
Van den Bout, David E. ; Miller, Thomas K., III
Author_Institution :
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
fDate :
5/1/1989 12:00:00 AM
Abstract :
A digital architecture which uses stochastic logic for simulating the behavior of Hopfield neural networks is described. This stochastic architecture provides massive parallelism (since stochastic logic is very space-efficient), reprogrammability (since synaptic weights are stored in digital shift registers), large dynamic range (by using either fixed- or floating-point weights), annealing (by coupling variable neuron gains with noise from stochastic arithmetic), high execution speed (≈N×108 connections per second), expandability (by cascading of multiple chips to host large networks), and practicality (by building with very conservative MOS device technologies). Results of simulations are given which show the stochastic architecture gives results similar to those found using standard analog neural networks or simulated annealing
Keywords :
MOS integrated circuits; digital simulation; integrated logic circuits; neural nets; parallel architectures; Hopfield neural nets; Hopfield neural networks; annealing; artificial neural networks; cascading of multiple chips; conservative MOS device technologies; digital architecture; digital shift registers; expandability; fixed point weights; floating-point weights; high execution speed; large dynamic range; massive parallelism; noise from stochastic arithmetic; practicality; reprogrammability; simulation; space-efficient; stochastic architecture; stochastic logic; stochasticism; synaptic weights; variable neuron gains; Annealing; Digital arithmetic; Dynamic range; Gain; Hopfield neural networks; Logic; Neurons; Shift registers; Stochastic processes; Stochastic resonance;
Journal_Title :
Circuits and Systems, IEEE Transactions on
