Analysis and proposal of signature circuits for LSI testing

A novel signature analysis method for LSI testing using multiple-input signature registers (MISRs) is presented. First, the double-bit and triple-bit error-detecting probabilities are analyzed theoretically in the case in which a single MISR defined by a primitive polynomial is used for a signature circuit. Second, to enhance the capability of detecting multiple errors contained in testing patterns, signature circuits are proposed that use multiplexed MISRs based on Reed-Solomon codes. It is proved that d-times multiplexed MISR can detect up to d symbol errors. Third, to reduce the amount of testing time, other signature circuits are proposed that use bit-width compression based on random error-detecting codes and multiplexed MISRs