• DocumentCode
    1160644
  • Title

    On single row routing

  • Author

    Saxena, Sanjeev ; Prasad, V.C.

  • Author_Institution
    Indian Inst. of Technol., New Delhi, India
  • Volume
    36
  • Issue
    7
  • fYear
    1989
  • fDate
    7/1/1989 12:00:00 AM
  • Firstpage
    1029
  • Lastpage
    1032
  • Abstract
    A parallel algorithm for the single-row routing problem without backward moves and interstreet crossings is presented. The algorithm requires O(log N log log N) time with N processors on a concurrent-read-concurrent-write shared-memory model or alternatively O(log2 N) time with N processors on a concurrent-read-exclusive-write shared-memory model. The algorithm is then modified to run sequentially in O(N) time
  • Keywords
    circuit layout CAD; parallel algorithms; concurrent-read-concurrent-write shared-memory model; concurrent-read-exclusive-write shared-memory model; parallel algorithm; single row routing; Circuits and systems; Computer science; Conductors; Read-write memory; Routing;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0098-4094
  • Type

    jour

  • DOI
    10.1109/31.31342
  • Filename
    31342
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1160644