Multiple fault detection using single fault test sets

Author

Hughes, Joseph L A

Author_Institution

Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

Volume

7

Issue

1

fYear

1988

fDate

1/1/1988 12:00:00 AM

Firstpage

100

Lastpage

108

Abstract

A simulation study of the 74LS181 4-b ALU (arithmetic logic unit) using 16 complete single stuck-at fault test sets demonstrated significantly higher multiple stuck-at fault coverage than predicted by previous theoretical studies. Analysis of the undetected multiple faults shows the effect of circuit and test set characteristics on fault coverage. A fault masking property, defined as self-masking, is observed for the undetected faults in the simulation study. A heuristic is described for evaluating the multiple fault coverage of single stuck-at fault test sets. A second heuristic generates augmented test sets, providing improved multiple stuck-at fault coverage with a minimal increase in test set development cost

Keywords

fault tolerant computing; logic testing; 74LS181 4-b ALU; arithmetic logic unit; fault coverage; fault masking property; heuristic; multiple fault coverage; multiple fault detection; self-masking; simulation study; single fault test sets; single stuck-at fault test sets; undetected faults; Circuit faults; Circuit simulation; Circuit testing; Costs; Digital circuits; Electrical fault detection; Fault detection; Logic circuits; Predictive models; Very large scale integration;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.3137

Filename

3137