Design techniques for a pipelined ADC without using a front-end sample-and-hold amplifier

Author

Chang, Dong-Young

Author_Institution

Texas Instrum. Inc., Tucson, AZ, USA

Volume

51

Issue

11

fYear

2004

Firstpage

2123

Lastpage

2132

Abstract

Design techniques for a low-power pipelined analog-to-digital converters (ADC) without using a front-end sample-and-hold amplifier are presented. Two sampling topologies are compared that minimize aperture error by matching the time constant between signal paths. A digital correction expansion technique is also presented for multibit ADCs, which further increases tolerance to aperture error. Elimination of the front-end SHA can save more than half of the ADCs static power dissipation.

Keywords

analogue-digital conversion; error correction; low-power electronics; pipeline processing; analog-to-digital converters; aperture error; digital correction expansion technique; pipelined ADC; sample-and-hold amplifier; signal paths; static power dissipation; time constant; Analog-digital conversion; Apertures; Delay; Error correction; Frequency; Instruments; Power dissipation; Preamplifiers; Sampling methods; Threshold voltage; 211;digital; 65; A/D; Amplifier; SHA; analog&#; aperture error; conversion; digital correction; low power; sample-and-hold amplifier; time constant;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2004.836842

Filename

1356143