Test generation of C-testable array dividers

With respect to the regular and iterative structure of iterative logic arrays (ILAs), the C-testable design that can be tested with a set of constant length irrespective of the circuit size has been presented. In the paper the concept of C-testability developed for ILAs is applied to the design of C-testable array dividers. The results show that the proposed nonrestoring and restoring array dividers are C-testable and can be fully tested using only 20 and 40 test patterns, respectively, irrespective of the array size. The innovative feature of the proposed test-generation scheme is that the generated patterns are constructed by repetitive and simple patterns that can be easily produced by a set of labels. Algorithms that generate the test patterns and expected outputs are also provided in detail.